# Fpga Hardware Design And Review Guide

> >

- **Type:** Skill
- **Install:** `agentstack add skill-cobbpeng-fpga-hardware-design-and-review-guide-fpga-hardware-design-and-review-guide`
- **Verified:** Yes — security-reviewed for prompt injection and unsafe behavior
- **Seller:** [cobbpeng](https://agentstack.voostack.com/s/cobbpeng)
- **Installs:** 0
- **Category:** [Agent Skills](https://agentstack.voostack.com/c/agent-skills)
- **Latest version:** 0.1.0
- **License:** MIT
- **Upstream author:** [cobbpeng](https://github.com/cobbpeng)
- **Source:** https://github.com/cobbpeng/fpga-hardware-design-and-review-guide
- **Website:** https://github.com/cobbpeng/fpga-hardware-design-and-review-guide

## Install

```sh
agentstack add skill-cobbpeng-fpga-hardware-design-and-review-guide-fpga-hardware-design-and-review-guide
```

Requires the [AgentStack CLI](https://agentstack.voostack.com/docs/cli). Works with Claude Code, Cursor, and any MCP-compatible agent.

## About

# FPGA Hardware Design Guide

A practical FPGA hardware design guide based on real-world project experience.

## Core Design Philosophy

### 1. Pipeline Architecture First

When processing high-speed data streams (video, network packets), adopt multi-stage pipeline design:
- **Single-stage processing**: Combinational logic delay too large, prone to timing violations
- **Multi-stage pipeline**: Insert registers at each stage, distribute delay, increase clock frequency
- **Typical applications**: RGB-to-YUV conversion, image filtering, protocol parsing

**Real Case**: RGB-to-YUV converter with 5-stage pipeline
- Stage 0: Input register (synchronize input signals)
- Stage 1: Multiply operation (coefficient * pixel value)
- Stage 2: Partial accumulation (R*coef_r + G*coef_g)
- Stage 3: Final accumulation (+ B*coef_b)
- Stage 4: Shift and saturation (truncate result to 8-bit)

### 2. The Art of Bit-Width Management

**Bit-width calculation principles**:
```
Multiplication bit-width = input bit-width + coefficient bit-width + 1 (sign bit)
Accumulation bit-width = multiplication bit-width + log2(number of additions) + 1 (guard bit)
```

**Rules of thumb**:
- 8-bit unsigned * 9-bit signed coefficient = 18-bit signed result
- 3 numbers of 18-bit addition = 20-bit (leave 2 guard bits to prevent overflow)
- After right-shifting 8 bits = 8-bit final result

### 3. Iron Rules of Synchronous Design

**Rules that must be followed**:
1. **All flip-flops use the same clock domain** (unless CDC is explicitly needed)
2. **Synchronous reset preferred over asynchronous reset** (avoid metastability propagation)
3. **Input signals must be registered for two cycles** (cross-clock domain or external inputs)
4. **Combinational logic outputs must be registered** (avoid glitch propagation)

**Lessons learned**:
- Asynchronous reset leads to unpredictable behavior when clock is unstable
- Unregistered combinational outputs may produce glitches after place-and-route
- Direct use of cross-clock domain signals causes metastability

## Timing Closure Practical Techniques

### Delay Analysis and Optimization

**Identifying critical paths**:
1. Check `Worst Negative Slack (WNS)` in synthesis report
2. Analyze `Total Negative Slack (TNS)` distribution
3. Locate logic levels with maximum delay

**Optimization strategies**:
1. **Insert pipeline registers** (most effective)
   - Insert FF in the middle of combinational logic
   - Each stage delay  16 (typically)
- Dual-port access required
- Large lookup tables (>1KB)

**When to use distributed RAM**:
- Small storage (<16 depth)
- Asynchronous read needed
- Save BRAM resources

**Code example**:
```systemverilog
// Automatically inferred as BRAM (36Kb block)
reg [7:0] mem [0:1023];  // 8Kbits
always @(posedge clk) begin
    if (we) mem[addr] <= din;
    dout <= mem[addr];  // Synchronous read
end

// Small capacity automatically uses LUTRAM
reg [7:0] small_mem [0:15];  // 128bits
```

### DSP Slice Optimization

**Fully utilize DSP48E1**:
- 25×18 multiplier (supports signed/unsigned)
- 48-bit accumulator
- Pre-adder (for symmetric FIR filters)

**Avoid DSP waste**:
- Don't use DSP for small multiplications (<8bit), LUTs are more efficient
- Use dedicated routing (ACIN/ACOUT) when cascading DSPs
- Use CE and SCLR controls to save power

## Debugging and Verification Methods

### Simulation Strategy

**Three-level verification system**:
1. **Behavioral simulation** (pre-synthesis)
   - Verify algorithm correctness
   - Use ideal delay models
   
2. **Post-synthesis simulation**
   - Verify synthesis result functionality
   - Check rough timing estimates
   
3. **Post-implementation simulation**
   - Include actual routing delays
   - Closest to real hardware

**Testbench writing essentials**:
```systemverilog
// 1. Self-checking test
initial begin
    // Apply stimulus
    apply_stimulus();
    
    // Wait for processing
    repeat(10) @(posedge clk);
    
    // Check results
    if (dout !== expected) begin
        $error("Test failed! Expected %h, got %h", expected, dout);
        $finish;
    end
    $display("Test passed!");
end

// 2. Coverage check
covergroup cg @(posedge clk);
    coverpoint state {
        bins idle = {IDLE};
        bins busy = {BUSY};
        bins done = {DONE};
    }
endgroup
```

### On-board Debugging Techniques

**Using ILA (Integrated Logic Analyzer)**:
1. Mark critical signals as `mark_debug`
2. Set trigger conditions (e.g., error flags, specific states)
3. Capture data to Vivado for analysis

**Using VIO (Virtual Input/Output)**:
- Modify parameters in real-time (e.g., filter coefficients)
- Monitor internal status registers
- Debug without recompilation

**Real debugging case**:
- Issue: YUV output occasionally shows wrong values
- Method: ILA captured multiplication intermediate results
- Finding: Sign extension error caused high-bit overflow
- Solution: Fixed signed number extension logic

## Reference Documentation

**Detailed design patterns**: See `references/design-patterns.md`
- CDC synchronizer design
- FIFO implementation
- AXI-Stream interface

**Common issues troubleshooting**: See `references/troubleshooting.md`
- Timing violation diagnosis process
- Metastability handling
- Resource conflict resolution

**Device selection guide**: See `references/device-selection.md`
- Selection based on resource requirements
- Package and speed grade selection
- Cost optimization suggestions

## Golden Rules

1. **Function first, optimization second** — Make the design work correctly first, then optimize timing and resources
2. **Constrain early, relax late** — Strict timing constraints early, relax based on situation later
3. **Register all boundaries** — Module inputs and outputs must be registered to avoid timing coupling
4. **Documentation is code** — Clear comments and documentation are more important than complex designs
5. **Test-driven development** — Write testbench first, then implement functionality

---

*This guide is based on real-world project experience and is continuously updated.*

Fix YAML syntax - add missing name field

## Source & license

This open-source skill is cataloged on AgentStack and links to its original source — we do not rehost the code.

- **Author:** [cobbpeng](https://github.com/cobbpeng)
- **Source:** [cobbpeng/fpga-hardware-design-and-review-guide](https://github.com/cobbpeng/fpga-hardware-design-and-review-guide)
- **License:** MIT
- **Homepage:** https://github.com/cobbpeng/fpga-hardware-design-and-review-guide

Install and usage instructions live in the source repository linked above.

## Pricing

- **Free** — Free

## Security capabilities

Automated source analysis of v0.1.0 — what this tool can access:

- **Network access:** no
- **Filesystem access:** no
- **Shell / process execution:** no
- **Environment & secrets:** no
- **Dynamic code execution:** no

*"Yes" means the capability is present in the source — more access means more to trust, not that it is unsafe.*


## Versions

- **0.1.0** — security scan: passed — Imported from the upstream source.

## Links

- Listing page: https://agentstack.voostack.com/l/skill-cobbpeng-fpga-hardware-design-and-review-guide-fpga-hardware-design-and-review-guide
- Seller: https://agentstack.voostack.com/s/cobbpeng
- Browse the marketplace: https://agentstack.voostack.com/browse

---
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