# Rtl Design Engineer

> Design, adapt, or package synthesizable RTL into meaningful clean testcases or reusable modules. Use when the user wants a new RTL block, wants to trim an existing open-source design into a standalone module, or needs a macro-free testcase with real functionality for synthesis/place/CTS experiments.

- **Type:** Skill
- **Install:** `agentstack add skill-mr-fang-vlsi-edagent-rtl-design-engineer`
- **Verified:** Yes — security-reviewed for prompt injection and unsafe behavior
- **Seller:** [Mr-Fang-VLSI](https://agentstack.voostack.com/s/mr-fang-vlsi)
- **Installs:** 0
- **Category:** [AI & ML](https://agentstack.voostack.com/c/ai-and-ml)
- **Latest version:** 0.1.0
- **License:** MIT
- **Upstream author:** [Mr-Fang-VLSI](https://github.com/Mr-Fang-VLSI)
- **Source:** https://github.com/Mr-Fang-VLSI/EDAgent/tree/main/skills/rtl-design-engineer

## Install

```sh
agentstack add skill-mr-fang-vlsi-edagent-rtl-design-engineer
```

Requires the [AgentStack CLI](https://agentstack.voostack.com/docs/cli). Works with Claude Code, Cursor, and any MCP-compatible agent.

## About

# RTL Design Engineer

## Role Boundary

This skill owns RTL-level work:
- selecting a realistic function block,
- building or trimming the RTL dependency closure,
- enforcing synthesizability and macro-free testcase constraints,
- and handing off a clean testcase package to synthesis / P&R flow.

This skill does **not** own final P&R conclusions. After testcase packaging, execution returns to `workflow-scoped-execution` or stage flows.

## Use This Skill When

Use this skill for requests such as:
- "build a clean testcase with no macro",
- "extract a meaningful RTL submodule from an open-source design",
- "design a standalone UART/AES/FIFO/router testcase",
- "prepare RTL that is synthesis-ready and suitable for placement/CTS experiments",
- "remove black-box or memory-macro dependencies from a testcase".

## Inputs

Provide or derive:
1. target function or candidate source RTL,
2. realism requirement (`real function`, not toy-only),
3. clean testcase constraints,
4. expected output contract.

## Output Contract

Return:
1. chosen testcase name,
2. why it is realistic,
3. why it is macro-free,
4. package paths,
5. unresolved risks before synthesis.

## Operational References

1. `references/clean-testcase-contract.md`
2. `references/testcase-workflow.md`
3. `references/package-and-validation.md`

## Source & license

This open-source skill is cataloged on AgentStack and links to its original source — we do not rehost the code.

- **Author:** [Mr-Fang-VLSI](https://github.com/Mr-Fang-VLSI)
- **Source:** [Mr-Fang-VLSI/EDAgent](https://github.com/Mr-Fang-VLSI/EDAgent)
- **License:** MIT

Install and usage instructions live in the source repository linked above.

## Pricing

- **Free** — Free

## Security capabilities

Automated source analysis of v0.1.0 — what this tool can access:

- **Network access:** no
- **Filesystem access:** no
- **Shell / process execution:** no
- **Environment & secrets:** no
- **Dynamic code execution:** no

*"Yes" means the capability is present in the source — more access means more to trust, not that it is unsafe.*


## Versions

- **0.1.0** — security scan: passed — Imported from the upstream source.

## Links

- Listing page: https://agentstack.voostack.com/l/skill-mr-fang-vlsi-edagent-rtl-design-engineer
- Seller: https://agentstack.voostack.com/s/mr-fang-vlsi
- Browse the marketplace: https://agentstack.voostack.com/browse

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Listed on AgentStack — the marketplace for AI agent skills and MCP servers. Every listing is security-reviewed. Creators keep 70%.