# Reviewing Vhdl

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- **Type:** Skill
- **Install:** `agentstack add skill-outcomeeng-claude-reviewing-vhdl`
- **Verified:** Yes — security-reviewed for prompt injection and unsafe behavior
- **Seller:** [outcomeeng](https://agentstack.voostack.com/s/outcomeeng)
- **Installs:** 0
- **Category:** [Agent Skills](https://agentstack.voostack.com/c/agent-skills)
- **Latest version:** 0.1.0
- **License:** MIT
- **Upstream author:** [outcomeeng](https://github.com/outcomeeng)
- **Source:** https://github.com/outcomeeng/claude/tree/main/plugins/hdl/skills/reviewing-vhdl

## Install

```sh
agentstack add skill-outcomeeng-claude-reviewing-vhdl
```

Requires the [AgentStack CLI](https://agentstack.voostack.com/docs/cli). Works with Claude Code, Cursor, and any MCP-compatible agent.

## About

Review hand-written VHDL through the lens of an experienced FPGA/ASIC engineer who writes idiomatic, synthesizable VHDL-2008. Produce prioritized findings covering library usage, type discipline, process patterns, naming conventions, and synthesizability.

Invoke: `/reviewing-vhdl`

Provide the VHDL files you want reviewed (design files, packages, testbenches, or any combination). The skill walks through a structured review:

1. **Library & Type Review** - IEEE library usage, type discipline, package organization
2. **Process & Structural Review** - Process patterns, FSMs, entity/architecture idioms
3. **Synthesizability & Style Review** - Latch detection, naming, readability
4. **Findings Report** - Prioritized improvements with idiomatic alternatives

**ieee.numeric_std is the only arithmetic library.** `std_logic_arith`, `std_logic_unsigned`, and `std_logic_signed` are Synopsys packages, not IEEE standard. Their presence is always a finding.

**std_ulogic over std_logic for single-driver signals.** `std_logic` is resolved (supports multiple drivers). Most signals have one driver. Use `std_ulogic` / `std_ulogic_vector` unless multi-driver resolution is required.

**Named association, always.** Positional port maps and generic maps are fragile and unreadable. Named association is non-negotiable.

**Complete assignments prevent latches.** Every branch of an `if` or `case` must assign every signal that any branch assigns. Missing assignments infer latches in synthesis.

**rising_edge() over 'event.** `clk'event and clk = '1'` fails on transitions from `'X'` to `'1'`. `rising_edge(clk)` is correct.

**Synchronous reset in the clocked process.** Asynchronous resets require careful CDC handling and complicate timing analysis. Prefer synchronous unless the target fabric demands otherwise.

What would you like reviewed?

Provide any combination of:

- **Design files** (.vhd) - Entities, architectures, component declarations
- **Package files** (.vhd) - Type definitions, constants, functions
- **Testbench files** (.vhd) - Stimulus generation, checking logic
- **Constraint files** (.xdc, .sdc) - Timing and placement constraints (for context)

You can provide file paths, paste code, or point to a directory.

**Wait for the user to provide files before proceeding.**

After the user provides files, execute the review workflow:

Read `${SKILL_DIR}/references/vhdl-idioms.md` first, then follow `${SKILL_DIR}/workflows/vhdl-review.md` exactly.

| User Provides   | Reference to Read                        | Additional Context                       |
| --------------- | ---------------------------------------- | ---------------------------------------- |
| Design files    | `${SKILL_DIR}/references/vhdl-idioms.md` | Full review against all idiom categories |
| Package files   | `${SKILL_DIR}/references/vhdl-idioms.md` | Focus on type discipline, naming         |
| Testbench files | `${SKILL_DIR}/references/vhdl-idioms.md` | Testbench-specific idioms apply          |
| Mixed           | `${SKILL_DIR}/references/vhdl-idioms.md` | Review each file in its appropriate mode |

| File                                     | Purpose                                           |
| ---------------------------------------- | ------------------------------------------------- |
| `${SKILL_DIR}/references/vhdl-idioms.md` | Comprehensive idiomatic VHDL-2008 reference       |
| `${SKILL_DIR}/workflows/vhdl-review.md`  | Step-by-step review procedure with finding format |

Review is complete when:

- [ ] Every file reviewed against idiomatic VHDL standards
- [ ] Findings are specific: file, line, what, why, idiomatic alternative
- [ ] Findings are prioritized: P0 (incorrect hardware), P1 (quality/maintainability), P2 (style)
- [ ] Non-standard library usage flagged
- [ ] Latch and sensitivity-list issues identified
- [ ] Naming convention deviations noted
- [ ] Summary table of all findings delivered

## Source & license

This open-source skill is cataloged on AgentStack and links to its original source — we do not rehost the code.

- **Author:** [outcomeeng](https://github.com/outcomeeng)
- **Source:** [outcomeeng/claude](https://github.com/outcomeeng/claude)
- **License:** MIT

Install and usage instructions live in the source repository linked above.

## Pricing

- **Free** — Free

## Security capabilities

Automated source analysis of v0.1.0 — what this tool can access:

- **Network access:** no
- **Filesystem access:** no
- **Shell / process execution:** no
- **Environment & secrets:** no
- **Dynamic code execution:** no

*"Yes" means the capability is present in the source — more access means more to trust, not that it is unsafe.*


## Versions

- **0.1.0** — security scan: passed — Imported from the upstream source.

## Links

- Listing page: https://agentstack.voostack.com/l/skill-outcomeeng-claude-reviewing-vhdl
- Seller: https://agentstack.voostack.com/s/outcomeeng
- Browse the marketplace: https://agentstack.voostack.com/browse

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Listed on AgentStack — the marketplace for AI agent skills and MCP servers. Every listing is security-reviewed. Creators keep 70%.