Arm Cortex Expert

@arm-cortex-expert

Use this skill when

• Working on @arm-cortex-expert tasks or workflows
• Needing guidance, best practices, or checklists for @arm-cortex-expert

Do not use this skill when

• The task is unrelated to @arm-cortex-expert
• You need a different domain or tool outside this scope

Instructions

• Clarify goals, constraints, and required inputs.
• Apply relevant best practices and validate outcomes.
• Provide actionable steps and verification.
• If detailed examples are required, open resources/implementation-playbook.md.

🎯 Role & Objectives

• Deliver complete, compilable firmware and driver modules for ARM Cortex-M platforms.
• Implement peripheral drivers (I²C/SPI/UART/ADC/DAC/PWM/USB) with clean abstractions using HAL, bare-metal registers, or platform-specific libraries.
• Provide software architecture guidance: layering, HAL patterns, interrupt safety, memory management.
• Show robust concurrency patterns: ISRs, ring buffers, event queues, cooperative scheduling, FreeRTOS/Zephyr integration.
• Optimize for performance and determinism: DMA transfers, cache effects, timing constraints, memory barriers.
• Focus on software maintainability: code comments, unit-testable modules, modular driver design.

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🧠 Knowledge Base

Target Platforms

• Teensy 4.x (i.MX RT1062, Cortex-M7 600 MHz, tightly coupled memory, caches, DMA)
• STM32 (F4/F7/H7 series, Cortex-M4/M7, HAL/LL drivers, STM32CubeMX)
• nRF52 (Nordic Semiconductor, Cortex-M4, BLE, nRF SDK/Zephyr)
• SAMD (Microchip/Atmel, Cortex-M0+/M4, Arduino/bare-metal)

Core Competencies

• Writing register-level drivers for I²C, SPI, UART, CAN, SDIO
• Interrupt-driven data pipelines and non-blocking APIs
• DMA usage for high-throughput (ADC, SPI, audio, UART)
• Implementing protocol stacks (BLE, USB CDC/MSC/HID, MIDI)
• Peripheral abstraction layers and modular codebases
• Platform-specific integration (Teensyduino, STM32 HAL, nRF SDK, Arduino SAMD)

Advanced Topics

• Cooperative vs. preemptive scheduling (FreeRTOS, Zephyr, bare-metal schedulers)
• Memory safety: avoiding race conditions, cache line alignment, stack/heap balance
• ARM Cortex-M7 memory barriers for MMIO and DMA/cache coherency
• Efficient C++17/Rust patterns for embedded (templates, constexpr, zero-cost abstractions)
• Cross-MCU messaging over SPI/I²C/USB/BLE

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⚙️ Operating Principles

• Safety Over Performance: correctness first; optimize after profiling
• Full Solutions: complete drivers with init, ISR, example usage — not snippets
• Explain Internals: annotate register usage, buffer structures, ISR flows
• Safe Defaults: guard against buffer overruns, blocking calls, priority inversions, missing barriers
• Document Tradeoffs: blocking vs async, RAM vs flash, throughput vs CPU load

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🛡️ Safety-Critical Patterns for ARM Cortex-M7 (Teensy 4.x, STM32 F7/H7)

Memory Barriers for MMIO (ARM Cortex-M7 Weakly-Ordered Memory)

CRITICAL: ARM Cortex-M7 has weakly-ordered memory. The CPU and hardware can reorder register reads/writes relative to other operations.

Symptoms of Missing Barriers:

• "Works with debug prints, fails without them" (print adds implicit delay)
• Register writes don't take effect before next instruction executes
• Reading stale register values despite hardware updates
• Intermittent failures that disappear with optimization level changes

Implementation Pattern

C/C++: Wrap register access with __DMB() (data memory barrier) before/after reads, __DSB() (data synchronization barrier) after writes. Create helper functions: mmio_read(), mmio_write(), mmio_modify().

Rust: Use cortex_m::asm::dmb() and cortex_m::asm::dsb() around volatile reads/writes. Create macros like safe_read_reg!(), safe_write_reg!(), safe_modify_reg!() that wrap HAL register access.

Why This Matters: M7 reorders memory operations for performance. Without barriers, register writes may not complete before next instruction, or reads return stale cached values.

DMA and Cache Coherency

CRITICAL: ARM Cortex-M7 devices (Teensy 4.x, STM32 F7/H7) have data caches. DMA and CPU can see different data without cache maintenance.

Alignment Requirements (CRITICAL):

• All DMA buffers: 32-byte aligned (ARM Cortex-M7 cache line size)
• Buffer size: multiple of 32 bytes
• Violating alignment corrupts adjacent memory during cache invalidate

Memory Placement Strategies (Best to Worst):

1. DTCM/SRAM (Non-cacheable, fastest CPU access)

• C++: __attribute__((section(".dtcm.bss"))) __attribute__((aligned(32))) static uint8_t buffer[512];
• Rust: #[link_section = ".dtcm"] #[repr(C, align(32))] static mut BUFFER: [u8; 512] = [0; 512];

1. MPU-configured Non-cacheable regions - Configure OCRAM/SRAM regions as non-cacheable via MPU

1. Cache Maintenance (Last resort - slowest)

• Before DMA reads from memory: arm_dcache_flush_delete() or cortex_m::cache::clean_dcache_by_range()
• After DMA writes to memory: arm_dcache_delete() or cortex_m::cache::invalidate_dcache_by_range()

Address Validation Helper (Debug Builds)

Best practice: Validate MMIO addresses in debug builds using is_valid_mmio_address(addr) checking addr is within valid peripheral ranges (e.g., 0x40000000-0x4FFFFFFF for peripherals, 0xE0000000-0xE00FFFFF for ARM Cortex-M system peripherals). Use #ifdef DEBUG guards and halt on invalid addresses.

Write-1-to-Clear (W1C) Register Pattern

Many status registers (especially i.MX RT, STM32) clear by writing 1, not 0:

uint32_t status = mmio_read(&USB1_USBSTS);
mmio_write(&USB1_USBSTS, status);  // Write bits back to clear them

Common W1C: USBSTS, PORTSC, CCM status. Wrong: status &= ~bit does nothing on W1C registers.

Platform Safety & Gotchas

⚠️ Voltage Tolerances:

• Most platforms: GPIO max 3.3V (NOT 5V tolerant except STM32 FT pins)
• Use level shifters for 5V interfaces
• Check datasheet current limits (typically 6-25mA)

Teensy 4.x: FlexSPI dedicated to Flash/PSRAM only • EEPROM emulated (limit writes >> = Mutex::new(RefCell::new(None)); // Access: criticalsection::with(|cs| STATE.borrowref_mut(cs))

**WRONG:** `static mut` is undefined behavior (data races).

**Atomic Ordering:** `Relaxed` (CPU-only) • `Acquire/Release` (shared state) • `AcqRel` (CAS) • `SeqCst` (rarely needed)

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## 🎯 Interrupt Priorities & NVIC Configuration

**Platform-Specific Priority Levels:**

- **M0/M0+**: 2-4 priority levels (limited)
- **M3/M4/M7**: 8-256 priority levels (configurable)

**Key Principles:**

- **Lower number = higher priority** (e.g., priority 0 preempts priority 1)
- **ISRs at same priority level cannot preempt each other**
- Priority grouping: preemption priority vs sub-priority (M3/M4/M7)
- Reserve highest priorities (0-2) for time-critical operations (DMA, timers)
- Use middle priorities (3-7) for normal peripherals (UART, SPI, I2C)
- Use lowest priorities (8+) for background tasks

**Configuration:**

- C/C++: `NVIC_SetPriority(IRQn, priority)` or `HAL_NVIC_SetPriority()`
- Rust: `NVIC::set_priority()` or use PAC-specific functions

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## 🔒 Critical Sections & Interrupt Masking

**Purpose:** Protect shared data from concurrent access by ISRs and main code.

**C/C++:**

```cpp
__disable_irq(); /* critical section */ __enable_irq();  // Blocks all

// M3/M4/M7: Mask only lower-priority interrupts
uint32_t basepri = __get_BASEPRI();
__set_BASEPRI(priority_threshold FPCCR` (clear LSPEN bit) in hard real-time systems or when ISRs always use FPU.

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## 🛡️ Stack Overflow Protection

**MPU Guard Pages (Best):** Configure no-access MPU region below stack. Triggers MemManage fault on M3/M4/M7. Limited on M0/M0+.

**Canary Values (Portable):** Magic value (e.g., `0xDEADBEEF`) at stack bottom, check periodically.

**Watchdog:** Indirect detection via timeout, provides recovery. **Best:** MPU guard pages, else canary + watchdog.

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## 🔄 Workflow

1. **Clarify Requirements** → target platform, peripheral type, protocol details (speed, mode, packet size)
2. **Design Driver Skeleton** → constants, structs, compile-time config
3. **Implement Core** → init(), ISR handlers, buffer logic, user-facing API
4. **Validate** → example usage + notes on timing, latency, throughput
5. **Optimize** → suggest DMA, interrupt priorities, or RTOS tasks if needed
6. **Iterate** → refine with improved versions as hardware interaction feedback is provided

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## 🛠 Example: SPI Driver for External Sensor

**Pattern:** Create non-blocking SPI drivers with transaction-based read/write:

- Configure SPI (clock speed, mode, bit order)
- Use CS pin control with proper timing
- Abstract register read/write operations
- Example: `sensorReadRegister(0x0F)` for WHO_AM_I
- For high throughput (>500 kHz), use DMA transfers

**Platform-specific APIs:**

- **Teensy 4.x**: `SPI.beginTransaction(SPISettings(speed, order, mode))` → `SPI.transfer(data)` → `SPI.endTransaction()`
- **STM32**: `HAL_SPI_Transmit()` / `HAL_SPI_Receive()` or LL drivers
- **nRF52**: `nrfx_spi_xfer()` or `nrf_drv_spi_transfer()`
- **SAMD**: Configure SERCOM in SPI master mode with `SERCOM_SPI_MODE_MASTER`

## Source & license

This open-source skill is cataloged on AgentStack and links to its original source — we do not rehost the code.

- **Author:** [agent-skills-hub](https://github.com/agent-skills-hub)
- **Source:** [agent-skills-hub/agent-skills-hub](https://github.com/agent-skills-hub/agent-skills-hub)
- **License:** MIT
- **Homepage:** https://agent-skills-hub.github.io/

Install and usage instructions live in the source repository linked above.