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SKILL verified MIT Self-run

Pcb Design

skill-maxpeng59-claude-pcb-design-skill-claude-pcb-design-skill · by Maxpeng59

Generate electrically-correct STM32-class PCB designs from real, orderable parts: a connectivity-correct netlist (pins mapped by function to actual chip pins), accurate footprints derived from real footprint-name geometry (never 'package not found'), a board render that looks like a fabricated 2-layer PCB (blue soldermask, gold pads, silkscreen, autorouted copper, GND pour, custom board outline),…

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Install

$ agentstack add skill-maxpeng59-claude-pcb-design-skill-claude-pcb-design-skill

✓ scanned · ✓ verified, works with Claude Code, Cursor, and more.

Security review

✓ Passed

No issues found. Passed automated security review. · v0.1.0 How review works →

  • Prompt-injection patterns
  • Secret / credential exfiltration
  • Dangerous shell & filesystem operations
  • Untrusted network calls
  • Known-malicious package signatures

What it can access

  • Network access No
  • Filesystem access No
  • Shell / process execution No
  • Environment & secrets No
  • Dynamic code execution No

From automated source analysis of v0.1.0. “Used” means the capability is present in the source — more access means more to trust, not that it’s unsafe.

View the full security report →

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Reliability & compatibility

Security review passed
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Declared compatibility

Claude CodeClaude Desktop

Compatibility is declared by the source manifest. End-to-end runtime verification is coming, see below.

Preview Execution monitoring

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About

PCB Design (v2 — real parts · routed render · firmware)

What this produces, and what it does not

From one pin-mapped design, the pipeline emits five consistent artifacts, all grounded in real orderable parts (each with a datasheet pinout, an LCSC C-number, and a real footprint-name that encodes its land pattern):

  1. Netlist (.net, KiCad-importable) — nets connect the **actual chip pins by

function** (all of an MCU's VDD/VSS, the real PB6 for I²C SCL). Not positional.

  1. Footprints (.kicad_mod) — pad geometry derived from the real footprint name

(LQFP-48_L7.0-W7.0-P0.50-LS9.0 → 7×7 body, 0.5 pitch, 9.0 span). Never "package not found."

  1. Board render (_board.png) — every footprint placed, a 2-layer grid

autorouter (MST + A*) routes the nets, a GND plane is poured, and it's drawn in the EDA 2D-view style: blue soldermask, gold ENIG pads, white silkscreen (outlines, pin-1, refdes, labels), vias, mounting holes, and a custom board outline (rounded-rect, quad-X flight controller, or gamepad silhouette).

  1. BOM (.bom.csv) — quantities + LCSC part numbers + footprints.
  2. Firmware (firmware/) — emits only the drivers the board has, with a

bsp.h pin map derived from and equal to the netlist.

Honest scope. This is the electrical layer + a believable board render, not a manufacturing-ready board. The autorouter is modest (~70–90% of nets; the remainder are drawn as honest ratsnest air-wires) — no impedance control, no rip-up/retry, no DRC sign-off. Import the netlist into LCEDA/KiCad and finish routing there. The firmware is structure- and pin-consistency-verified but not compiler-built (no ARM toolchain), so it's a correct scaffold, not certified binary. Do not claim it equals a hand-routed production board.

The design format

A design is components, each a catalog part + a pin_map of {real-pin-name: net}, a pos, and a rot. The same net name on two parts connects their real pins. The board has a w, h, and an outline (rounded, quad_x, or gamepad).

{"name": "My Board", "board": {"w": 88, "h": 88, "outline": "quad_x"},
 "components": [
   {"ref": "U1", "part": "mcu_stm32f103", "pos": {"x": 44, "y": 44}, "rot": 0,
    "pin_map": {"VDD": "3V3", "VSS": "GND", "PB6": "SCL", "PB7": "SDA",
                "PA5": "SCK", "PA6": "MISO", "PA7": "MOSI", "PA4": "NRF_CSN"}},
   {"ref": "U2", "part": "sens_mpu6050", "pos": {"x": 32, "y": 51},
    "pin_map": {"VDD": "3V3", "GND": "GND", "SCL": "SCL", "SDA": "SDA"}},
   ...
 ]}

pcbgen.core.PARTS lists available parts (STM32F103, MPU6050, SPL06, nRF24, XC6206 LDO, USB-C, crystal, YF16 joystick, KH-6×6 tactile, slide switch, AO4466 MOSFET, headers, 0402/0603/1206 passives, LEDs). Use only those part ids and pin names that exist on the part — the build reports any unknown part or pin.

Workflow

  1. Pick parts from pcbgen.core.PARTS; assign the MCU's peripherals to **valid

pins** (I²C on I²C pins, SPI on SPI pins, ADC for joysticks, etc.).

  1. Give every supply rail one consistent name, sourced and consumed (the build

flags dangling/unsourced rails).

  1. Add support parts: a decoupling cap per IC supply pin, I²C pull-ups, crystal load

caps, USB CC resistors, NRST pull-up.

  1. Place components sensibly on the chosen outline (MCU central, peripherals around).
  2. Run: python3 run.py path/to/design.(py|json) → netlist + BOM + footprints +

board render + firmware in out//.

  1. Import the netlist into LCEDA/KiCad and finish routing. Flash the firmware.

See examples/fc_quad.py (quadcopter FC) and examples/gamepad.py (RC transmitter) for two reference-grade, fully pin-mapped designs built only from real BOM parts.

Verification (always)

build() reports unknown parts/pins; connectivity_issues() flags dangling/unsourced rails — both must be empty. The firmware generator asserts every pin used in firmware is defined in bsp.h and equals the netlist. sim.py batch-grades many designs (netlist + footprints + render + firmware verdict). All must pass before you trust an output.

Source & license

This open-source skill is cataloged on AgentStack and links to its original source — we do not rehost the code.

Install and usage instructions live in the source repository linked above.

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Versions

  • v0.1.0 Imported from the upstream source.