Gpio Baremetal
Bare-metal GPIO skill for pin configuration and interrupts. Use when configuring GPIO modes, alternate functions, pull resistors, or EXTI interrupts on STM32/nRF/ESP32-class MCUs. Activates on queries about GPIO MODER, alternate function, pin interrupt, or LED/button bare-metal setup.
Install
$ agentstack add skill-mohitmishra786-low-level-dev-skills-gpio-baremetal ✓ scanned · ✓ verified, works with Claude Code, Cursor, and more.
Security review
✓ PassedNo issues found. Passed automated security review. · v0.1.0 How review works →
- ✓ Prompt-injection patterns
- ✓ Secret / credential exfiltration
- ✓ Dangerous shell & filesystem operations
- ✓ Untrusted network calls
- ✓ Known-malicious package signatures
What it can access
- ✓ Network access No
- ✓ Filesystem access No
- ✓ Shell / process execution No
- ✓ Environment & secrets No
- ✓ Dynamic code execution No
From automated source analysis of v0.1.0. “Used” means the capability is present in the source — more access means more to trust, not that it’s unsafe.
Verified badge
Passed review? Show it. Paste this badge into your README, it links to the public security report.
Links to your public security report.[](https://agentstack.voostack.com/security/report/skill-mohitmishra786-low-level-dev-skills-gpio-baremetal) Reliability & compatibility
Declared compatibility
Compatibility is declared by the source manifest. End-to-end runtime verification is coming, see below.
We're building live execution health for every listing: tool-call success rate, median latency, uptime, and last-checked timestamps, measured, not self-reported. It isn't live yet, so we don't show numbers we can't stand behind.
How agent discovery & health will work →About
GPIO (Bare-Metal)
Purpose
Configure and use GPIO without HAL: input/output modes, alternate function mapping, pull-up/down, speed/slew, and pin-change interrupts for LEDs, buttons, and peripheral pin mux.
When to Use
- Blink LED or read button before bringing up UART/SPI
- Mux pins to USART/SPI alternate functions
- EXTI line interrupts on pin edges
- Porting GPIO code between vendors
Workflow
1. STM32 GPIO pattern
/* Enable GPIOA clock */
RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN;
/* PA5 output — MODER[11:10] = 01 */
GPIOA->MODER &= ~(3U MODER |= (1U BSRR = (1U BSRR = (1U MODER &= ~(3U MODER |= (2U AFR[0] &= ~(0xFU AFR[0] |= (7U MODER &= ~(3U PUPDR &= ~(3U PUPDR |= (1U IDR & (1U EXTICR[3] = (SYSCFG->EXTICR[3] & ~0xFU) | 0x2; /* port C */
EXTI->IMR |= (1U FTSR |= (1U PR`, clear with write-1.
### 4. nRF52 / ESP32 notes
| Platform | Pattern |
|----------|---------|
| nRF52 | `NRF_P0->PIN_CNF[n]` — direction, pull, drive |
| ESP32 | `GPIO.out_w1ts`, `GPIO.enable`; IO_MUX for function |
Always enable peripheral clock / power domain before pin config.
### 5. Agent usage
/gpio-baremetal Configure PA2 as USART2 TX alternate function on STM32F4
## Common Problems
| Symptom | Cause | Fix |
|---------|-------|-----|
| Pin stuck | Wrong MODER / not AF | Re-read RM pin table |
| EXTI storm | No debounce / floating input | Enable pull; debounce in software |
| AF mismatch | Wrong AFR nibble | Pin-specific AF table in RM |
| No toggle visible | Wrong port bit / LED active low | Check schematic |
## Related Skills
- `skills/baremetal/mmio-and-bit-manipulation` — BSRR/MODER masks
- `skills/baremetal/peripherals-from-datasheet` — RM pinout tables
- `skills/baremetal/uart-serial-baremetal` — AF mux for serial
## Source & license
This open-source skill is cataloged on AgentStack and links to its original source — we do not rehost the code.
- **Author:** [mohitmishra786](https://github.com/mohitmishra786)
- **Source:** [mohitmishra786/low-level-dev-skills](https://github.com/mohitmishra786/low-level-dev-skills)
- **License:** MIT
- **Homepage:** https://www.lowleveldevskills.com
Install and usage instructions live in the source repository linked above.
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Versions
- v0.1.0 Imported from the upstream source.