Self-run
SKILL
Hdldiagzero
Generate validated SVG block diagrams for HDL/RTL/FPGA/SoC designs. Use when asked to draw, diagram, sketch, render, or visualize Verilog, SystemVerilog, VHDL, Vivado BD, or LiteX architecture. Produces JSON specs plus SVGs, color-codes clock domains, distinguishes AXI/MM/Lite/Stream and TileLink, and hides clock/reset/JTAG/debug detail by default.
0
3
Free Self-run
MCP
FpgaZeroMCP
An open-source Model Context Protocol server that gives AI assistants a complete FPGA toolchain — lint, simulate, synthesize, place-and-route, and a live IP core registry backed by GitHub.
0
5
Free You've reached the end · 2 loaded