Vtestgen
Scaffold a Makefile-driven, CPU-bus-controlled testbench project for an IP and generate a comprehensive set of self-checking testcases, validate each with make, and write a testcase list
Vdebug
Trace failing signals through the RTL hierarchy, classify root cause, and write a debug report per issue — no fix is proposed
Vfill
Implement Verilog code from an approved design proposal, then lint and simulate
Vdoc
Aggregate all per-module documentation into a single comprehensive IP document
Vtestrun
Run all IP-level testcases from tc_list.md through the bench Makefile, capture results, and write per-failure issue reports with no fix suggestions
Varch
Decompose an IP requirement into submodules, define interfaces, and generate an architecture document plus per-module requirement files and a top-level skeleton
Vflow
Scan project state to determine phase completion, write flow_status.md, and orchestrate the full RTL design flow from architecture to documentation
Vdesign
Generate a design proposal, documentation, and RTL backbone from a requirement file
Vexplain
Generate documentation for any RTL module from Verilog source files
Vsynth
Synthesize a Verilog module or full IP with Vivado and report resource utilization, Fmax, and power