Install
$ agentstack add skill-mohitmishra786-low-level-dev-skills-dma-baremetal ✓ scanned · ✓ verified, works with Claude Code, Cursor, and more.
Security review
✓ PassedNo issues found. Passed automated security review. · v0.1.0 How review works →
- ✓ Prompt-injection patterns
- ✓ Secret / credential exfiltration
- ✓ Dangerous shell & filesystem operations
- ✓ Untrusted network calls
- ✓ Known-malicious package signatures
What it can access
- ✓ Network access No
- ✓ Filesystem access No
- ✓ Shell / process execution No
- ✓ Environment & secrets No
- ✓ Dynamic code execution No
From automated source analysis of v0.1.0. “Used” means the capability is present in the source — more access means more to trust, not that it’s unsafe.
Verified badge
Passed review? Show it. Paste this badge into your README, it links to the public security report.
Reliability & compatibility
Declared compatibility
Compatibility is declared by the source manifest. End-to-end runtime verification is coming, see below.
We're building live execution health for every listing: tool-call success rate, median latency, uptime, and last-checked timestamps, measured, not self-reported. It isn't live yet, so we don't show numbers we can't stand behind.
How agent discovery & health will work →About
DMA (Bare-Metal)
Purpose
Configure DMA controllers for memory-to-peripheral and peripheral-to-memory transfers: channel/stream setup, burst sizes, circular mode, half-transfer interrupts, and cache coherency on Cortex-M7.
When to Use
- Offloading UART/SPI/ADC bulk transfers from CPU
- Audio/streaming double buffers
- Debugging DMA not triggering or corrupt data
Workflow
1. STM32 DMA2 stream (periph→mem)
/* UART2 RX DMA — Stream5, Channel 4 (verify RM matrix) */
RCC->AHB1ENR |= RCC_AHB1ENR_DMA1EN;
DMA1_Stream5->PAR = (uint32_t)&USART2->DR;
DMA1_Stream5->M0AR = (uint32_t)rx_buf;
DMA1_Stream5->NDTR = sizeof(rx_buf);
DMA1_Stream5->CR = DMA_SxCR_MINC /* mem increment */
| DMA_SxCR_TCIE /* transfer complete IRQ */
| DMA_SxCR_CHSEL_2 /* channel 4 */
| DMA_SxCR_EN;
USART2->CR3 |= USART_CR3_DMAR;
2. Circular / double buffer
DMA1_Stream5->CR |= DMA_SxCR_CIRC; /* auto-reload NDTR */
/* HTIF = first half, TCIF = second half — process in IRQ */
3. Cortex-M7 cache (H7)
DMA buffer in non-cacheable region or clean/invalidate D-Cache:
SCB_CleanDCache_by_Addr((void*)tx_buf, len);
/* after DMA TX */
SCB_InvalidateDCache_by_Addr((void*)rx_buf, len);
4. Agent usage
/dma-baremetal Configure UART RX DMA circular buffer on STM32F4
Common Problems
| Symptom | Cause | Fix | |---------|-------|-----| | DMA no start | Stream/channel mismatch | RM DMA request mapping table | | Corrupt RX | Cache coherency (M7) | Invalidate after RX complete | | NDTR stuck | Peripheral DMA enable missing | USART_CR3 DMAR/DMAT | | IRQ flood | Clear flags in ISR | DMA_LISR/HIFCR |
Related Skills
skills/baremetal/uart-serial-baremetal— USART DMA enableskills/baremetal/adc-dac-baremetal— ADC DMA modeskills/low-level-programming/cpu-cache-opt— cache line concepts
Source & license
This open-source skill is cataloged on AgentStack and links to its original source — we do not rehost the code.
- Author: mohitmishra786
- Source: mohitmishra786/low-level-dev-skills
- License: MIT
- Homepage: https://www.lowleveldevskills.com
Install and usage instructions live in the source repository linked above.
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Versions
- v0.1.0 Imported from the upstream source.